III-V semiconductor nanowires (planar)

Our group is interested in the growth and application of metal-seeded III-V nanowires grown with metalorganic chemical vapor deposition (MOCVD). We have discovered that under controlled growth conditions it is possible to grow "planar" III-V nanowires that self-align along <110> directions on (001) substrates and <100> directions on (110) substrates. Unlike out-of-plane <111> III-V nanowires, planar III-V nanowires are free of twin planes and stacking faults, and high in mobility. Furthermore, the self-alignment in the plane of the substrate makes planar III-V nanowires very suitable for integration with conventional planar processing techniques. Planar III-V nanowires are well positioned to bring out new applications in nanoelectronics and nanophotonics.

Planar III-V nanowire array based high speed transistor (Nano Letters: Cover, May 2015.)

False colored SEM image of a double-channel high electron mobility transistor (HEMT) built from an array of perfectly parallel planar GaAs nanowires grown from the bottom-up via the vapor-liquid-solid (VLS) mechanism. The connected double fingers (yellow) are the common gate that controls the electron flow from the sources (left and right brown pads) to the common drain (center brown pad). The channel is an array of 35 µm long undoped planar GaAs nanowires covered by a doped AlGaAs barrier layer (under the gate fingers). A highly doped GaAs layer (bluish grey) was kept on top of the AlGaAs barrier in the source/drain region for Ohmic contact formation. A 1.5 X 1.5 cm2 chip with 115 of such transistors are fabricated, where these transistors show record-breaking DC/RF performance and chip-level electrical uniformity.

Related publications

  • C. Zhang, X. Miao, K. Chabak, and X. Li, “A Review of III-V Planar Nanowire Arrays: Selective Lateral VLS Epitaxy and 3D Transistors," J. Phys. D: Appl. Phys. invited review, 2017.
  • C. Zhang, W. Choi, P. Mohseni, and X. Li, "InAs Planar Nanowire Gate-All-Around MOSFETs on GaAs Substrates by Selective Lateral Epitaxy," IEEE Electron Dev. Lett., 36(7), 663-665 (2015).[pdf]
  • K. D. Chabak, X. Miao, C. Zhang, D. E. Walker Jr., P. K. Mohseni, and X. Li, "RF Performance of Planar III-V Nanowire-Array Transistors Grown by Vapor-Liquid-Solid Epitaxy," IEEE Electron Device Lett. 36(5), 445-447 (2015).[pdf]
  • X. Miao, K. D. Chabak, C. Zhang, P. K. Mohseni, D. E. Walker Jr., and X. Li, "High Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth," Nano Letters, 15 (5), pp 2780-2786 (2015). [pdf] Selected as the cover image of May 2015 issue.
  • C. Zhang, X. Miao, P. K. Mohseni, W. Choi, and X. Li, "Site-Controlled Planar GaAs Nanowire Growth: Yield and Mechanism", Nano Letters, 14 (12), 6836 (2014). [pdf]
  • C. Zhang and X. Li, ''Planar GaAs Nanowire Tri-Gate MOSFETs by Vapor-Liquid-Solid Growth Solid State Electronics'', Solid State Electronics 93, 40 (2014). [pdf]
  • R. Dowdy, C. Zhang, P. K. Mohseni, S. A. Fortuna, J-G Wen, J. J. Coleman, and X. Li, ''Perturbation of Au-assisted Planar GaAs Nanowire Growth by p-Type Dopant Impurities'', Optical Materials Express Vol. 3, Issue 10, pp. 1687-1697 (2013). [pdf]
  • X. Miao, C. Zhang, and X. Li, "Monolithic Barrier-All-Around High Electron Mobility Transistor with Planar GaAs Nanowire Channel", Nano Letters 13 (6), 2548, (2013).[pdf]
  • R. S. Dowdy, D. A. Walko, and X. Li, "Relationship between plannar GaAs nanowire growth direction and substrate orientation" Nanotechnology 24, 035304 (2013).[pdf]
  • R. Dowdy, D. Walko, S. A. Fortuna, and X. Li, "Realization of Unidirectional Planar GaAs Nanowires on (110) Substrates", IEEE Electron Device Letters, 33, 522 (2012).[pdf]
  • X. Miao and X. Li, "Scalable Monolithically Grown AlGaAs-GaAs Planar Nanowire High-Electron-Mobility Transistor", IEEE Electron Device Letters 32, 1227-1229 (2011). [pdf]
  • S.A. Fortuna and X. Li, "Metal-catalyzed semiconductor nanowires: a review on the control of growth directions", Semicond. Sci. Technol. 25 (2010) 024005. [pdf]
  • S.A. Fortuna and X. Li, "Metal-catalyzed semiconductor nanowires: a review on the control of growth directions", Semicond. Sci. Technol. 25 (2010) 024005. [pdf]
  • S.A. Fortuna, and X. Li, "GaAs MESFET With a High-Mobility Self-Assembled Planar Nanowire Channel", IEEE Elec. Dev. Lett. 30 (6), 593-595 (2009). [pdf]
  • S.A. Fortuna, J. Wen, I.S. Chun, and X. Li, "Planar GaAs Nanowires on GaAs (100) Substrates: Self-Aligned, Nearly Twin-Defect Free, and Transfer-Printable", Nano Letters (2008). [pdf]

Planar III-V nanowire growth with MOCVD

Metal-seeded nanowires are grown using one of two MOCVD reactors available in the clean room at the MNTL building on the University of Illinois campus. Shown in Figure 2 is a schematic of the GaAs nanowire growth process. Au nanoparticles - used to seed III-V nanowire growth - are scattered on a (001) GaAs substrate. The substrate is then placed inside the MOCVD reactor and heated to the growth temperature (typically 400 - 520 °C). Nanowire growth is initiated through the introduction of suitable gas precursors such as trimethylgallium and arsine for the growth of GaAs nanowires. Within a growth temperature window of around 460 - 475 °C, planar GaAs nanowires grow epitaxially on the substrate surface and laterally along <110> directions in the plane of the substrate. Transmission electron microscopy has confirmed the nanowires are nearly defect-free.

Figure 2 -- Schematic of the growth of planar <110> GaAs nanowires on GaAs (001) substrates using MOCVD. A SEM image of two aligned 10 μm long planar GaAs nanowires is shown in the bottom panel.

Shown in Figure 3, the morphology of planar III-V nanowires is controlled primarily through growth temperature. At lower growth temperatures (450 °C or less) the nanowires mostly grow in the <111> directions out of the plane of the substrate. However, at higher growth temperatures (520 °C or higher), the nanowires have a tadpole-like shape due to increased deposition along the nanowire sidewalls.

Figure 3 -- Arrhenius plot of the nanowire growth rate showing how the morphology of III-V nanowires is primarily controlled through growth temperature. Reproduced with permission from American Chemical Society.

Highly-aligned III-V nanowires on silicon substrates

We have demonstrated a large-scale transfer of highly-aligned GaAs planar nanowires to silicon substrates. This is achieved by growing the GaAs nanowires on an epitaxial sacrificial AlGaAs layer. The AlGaAs layer is etched away leaving the planar nanowires untethered from the growth substrate. A PDMS stamp is then used to pick and place the untethered GaAs nanowires from the growth substrate to an arbitrary substrate (such as silicon). Shown in Figure 4 is the result of such a process where highly-aligned GaAs nanowires have been transferred to a silicon surface.

Figure 4 -- SEM of images highly-aligned <110> GaAs nanowires transferred to a silicon substrate. Reproduced with permission from American Chemical Society.

Planar III-V nanowire MESFET with high electron mobility

We fabricated a long-channel MESFET by utilizing a planar GaAs nanowire as the device channel (Figure 5). The GaAs nanowire was doped n-type with Si (disilane gas precursor, estimated doping of 2e17 cm-3) and grown on an semi-insulating (001) GaAs substrate. Gate and drain/source metalizations were created with standard processes. Electrical measurements shows well-defined long channel characteristics. Using a slightly modified long-channel MESFET model an electron mobility of μ = 4120 cm2/Vs was extracted from the measured data. This mobility matches closely with the electron mobility expected from a conventional thin-film device thus implying the planar nanowire has bulk-like transport characteristics.

Figure 5 -- Shown at the top is a false-color SEM image of a GaAs planar nanowire MESFET. The plot on the left shows the Ids-Vds family of curves. The plot on the right shows a good fit of measured to simulated data that was obtained with a slighly modified long-channel MESFET model. A bulk-like electron mobility of μ = 4120 cm2/Vs was extracted from the measured data.